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general description the MAX14950A dual equalizer/redriver improves pci express ? (pcie) signal integrity by providing program - mable input equalization. this feature reduces deter - ministic jitter and redrives circuitry to reestablish deem - phasis, which compensates for circuit-board loss at high frequencies. the device permits optimal placement of key pcie components and allows for longer runs of strip - line, microstrip, or cable. the device contains two identical channels capable of equalizing pcie gen iii (8gt/s), gen ii (5gt/s), and gen i (2.5gt/s) signals and features electrical idle and receiver detection. the MAX14950A is available in a small, 40-pin, 5.0mm x 5.0mm tqfn package with flow-through traces for optimal layout and minimal space requirements. it is specified over the 0 n c to +70 n c commercial operating temperature range. applications servers test equipment external graphics applications communications switchers storage area networks benefits and features s innovative design eliminates need for costly external components ? single +3.3v supply operation s increased design flexibility for backward- compatible applications ? optimized for pcie gen iii (8gt/s) and gen ii (5gt/s) signals and compatible with gen i (2.5gt/s) signals s high level of integration for performance ? random jitter: 0.5ps rms , deterministic jitter: 7ps p-p ? four-level-programmable input equalization ? eight-level-programmable output emphasis ? electrical idle detection ? receiver detection permits completely transparent operation s ideal for space-sensitive applications ? on-chip 50 i input/output terminations ? 40-pin, 5.0mm x 5.0mm tqfn packaging typical operating circuit 19-5965; rev 1; 4/13 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14950A.related . pci express is a registered service mark of pci-sig corporation. single differential pair single differential pair midplane remote board connectors tx rx main board pcie rx tx pcie MAX14950A MAX14950A single-lane pcie equalizer/redriver for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 (voltages referenced to gnd.) v cc ....................................................................... -0.3v to +4.0v all other pins (note 1) ............................. -0.3v to (v cc + 0.3v) continuous current in_p, in_m, out_p, out_m ........................................................... q 30ma peak current in_p, in_m, out_p, out_m (pulsed for 1 f s, 1% duty cycle) ................................ q 100ma continuous power dissipation (t a = +70 n c) tqfn (derate 35.7mw/ n c above +70 n c) .................. 2857mw operating temperature range ............................. 0 n c to +70 n c junction temperature range ........................... -40 n c to +150 n c storage temperature range ............................ -65 n c to +150 n c lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c tqfn junction-to-ambient thermal resistance ( b ja ) ......... 28 n c/w junction-to-case thermal resistance ( b jc ) ................. 2 n c/w absolute maximum ratings note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 2) electrical characteristics (v cc = +3.0v to +3.6v, c cl = 200nf coupling capacitor on each output, r l = 50 i on each output, t a = 0 n c to +70 n c, unless oth - erwise noted. typical values are at v cc = +3.3v and t a = +25 n c.) (note 3) note 1: all i/o pins are clamped by internal diodes. parameter symbol conditions min typ max units dc performance power-supply range v cc 3.0 3.3 3.6 v supply current i cc en = v cc oeq_2 = oeq_1 = oeq_0 = gnd 102 135 ma oeq_2 = oeq_1 = gnd, oeq_0 = v cc 106 140 oeq_2 = oeq_0 = gnd, oeq_1 = v cc 107 140 oeq_2 = gnd, oeq_1 = oeq_0 = v cc 125 160 oeq_2 = v cc , oeq_1 = oeq_0 = gnd 106 140 oeq_2 = oeq_0 = v cc , oeq_1 = gnd 132 170 oeq_2 = oeq_1 = v cc , oeq_0 = gnd 140 180 oeq_2 = oeq_1 = oeq_0 = v cc 165 210 MAX14950A single-lane pcie equalizer/redriver maxim integrated
3 electrical characteristics (continued) (v cc = +3.0v to +3.6v, c cl = 200nf coupling capacitor on each output, r l = 50 i on each output, t a = 0 n c to +70 n c, unless oth - erwise noted. typical values are at v cc = +3.3v and t a = +25 n c.) (note 3) parameter symbol conditions min typ max units standby current i stby en = gnd oeq_2 = oeq_1 = oeq_0 = gnd 57 80 ma oeq_2 = oeq_1 = gnd, oeq_0 = v cc 61 85 oeq_2 = oeq_0 = gnd, oeq_1 = v cc 62 85 oeq_2 = gnd, oeq_1 = oeq_0 = v cc 75 100 oeq_2 = v cc , oeq_1 = oeq_0 = gnd 62 80 oeq_2 = oeq_0 = v cc , oeq_1 = gnd 85 110 oeq_2 = oeq_1 = v cc , oeq_0 = gnd 92 120 oeq_2 = oeq_1 = oeq_0 = v cc 120 150 differential input impedance z rx-diff- dc dc 80 100 120 i differential output impedance z tx-diff- dc dc 80 100 120 i common-mode resistance to gnd, input termination not powered z rx-high- imp-dc -150mv p v in_cm p +200mv 50 k i common-mode resistance to gnd, input termination powered z rx-dc 20 25 30 i output short-circuit current i tx-short single-ended (note 4) 90 ma common-mode delta, between active and idle states v tx-cm- dc-active- idle-delta 100 mv dc output offset, during active state v tx- active- diff-dc |(v out_p - v out_m )| 65 mv dc output offset, during electrical idle v tx-idle- diff-dc |(v out_p - v out_m )| 65 mv MAX14950A single-lane pcie equalizer/redriver maxim integrated
4 electrical characteristics (continued) (v cc = +3.0v to +3.6v, c cl = 200nf coupling capacitor on each output, r l = 50 i on each output, t a = 0 n c to +70 n c, unless oth - erwise noted. typical values are at v cc = +3.3v and t a = +25 n c.) (note 3) parameter symbol conditions min typ max units ac performance (note 4) input return loss, differential rl rx-diff f = 0.05ghz to 1.25ghz 9 db f = 1.25ghz to 2.5ghz 8 db f = 2.5ghz to 4ghz 5 db input return loss, common mode rl rx-cm f = 0.05ghz to 2.5ghz 6 db f = 2.5ghz to 4ghz 4 db output return loss, differential rl tx-diff f = 0.05ghz to 1.25ghz 10 db f = 1.25ghz to 2.5ghz 8 db f = 2.5ghz to 4ghz 4 db output return loss, common mode rl tx-cm f = 0.05ghz to 2.5ghz 6 db f = 2.5ghz to 4ghz 4 db redriver-operation differential input-signal range v rx-diff- pp 100 1400 mv p-p full-swing differential output voltage (no deemphasis) v tx-diff- pp oeq_2 = oeq_1 = oeq_0 = gnd 800 1000 1400 mv p-p output deemphasis ratio, 0db v tx-de- ratio-0db oeq_2 = oeq_1 = oeq_0 = gnd, figure 1 0 db output deemphasis ratio, 3.5db v tx-de- ratio- 3.5db oeq_2 = oeq_1 = gnd, oeq_0 = v cc , figure 1 3.5 db output deemphasis ratio, 6db v tx-de- ratio-6db oeq_2 = oeq_0 = gnd, oeq_1 = v cc , figure 1 6 db output deemphasis ratio, 6db with higher amplitude v tx-de-ha- ratio-6db oeq_2 = gnd, oeq_1 = oeq_0 = v cc , figure 1 6 db output deemphasis ratio, 3.5db with preshoot v tx-de- ps-ratio- 3.5db oeq_2 = v cc , oeq_1 = oeq_0 = gnd, figure 1 3.5 db output deemphasis ratio, 6db with preshoot v tx-de-ps- ratio-6db oeq_2 = oeq_0 = v cc , oeq_1 = gnd, figure 1 6 db output deemphasis ratio, 9db with preshoot v tx-de-ps- ratio-9db oeq_2 = oeq_1 = v cc , oeq_0 = gnd, figure 1 9 db output deemphasis ratio, 9db with preshoot and higher amplitude v tx-de-ps- ha-ratio- 9db oeq_2 = oeq_1 = oeq_0 = v cc , figure 1 9 db input equalization, 5db v rx-eq- 5db ineq_1 = ineq_0 = gnd (note 5) 5 db MAX14950A single-lane pcie equalizer/redriver maxim integrated
5 electrical characteristics (continued) (v cc = +3.0v to +3.6v, c cl = 200nf coupling capacitor on each output, r l = 50 i on each output, t a = 0 n c to +70 n c, unless oth - erwise noted. typical values are at v cc = +3.3v and t a = +25 n c.) (note 3) parameter symbol conditions min typ max units input equalization, 8db v rx-eq- 8db ineq_1 = gnd, ineq_0 = v cc (note 5) 8 db input equalization, 12db v rx-eq- 12db ineq_1 = v cc , ineq_0 = gnd (note 5) 12 db input equalization, 16db v rx-eq- 16db ineq_1 = ineq_0 = v cc (note 5) 16 db output common-mode voltage v tx-cm- ac-pp max(v out_p + v out_m )/2 - min(v out_p + v out_m )/2 100 mv p-p propagation delay t pd 90 160 240 ps rise/fall time t tx-rise- fall (note 6) 20 ps rise/fall time mismatch t tx-rf- mismatch (note 6) 20 ps deterministic jitter t tx-dj-dd k28.5 pattern, ac-coupled, r l = 50 i , no deemphasis, no preshoot, data rate = 8gt/s 7 23.5 ps p-p random jitter t tx-rj-dd d10.2 pattern, no deemphasis, no preshoot, data rate = 8gt/s 0.5 1.5 ps rms electrical idle entry delay t tx-idle- set-to- idle from input to output, d10.2 pattern, data rate = 1gt/s 5 ns electrical idle exit delay t tx-idle- to-diff- data from input to output, d10.2 pattern, data rate = 1gt/s 5 ns electrical idle detect threshold v tx-idle- thresh d10.2 pattern, data rate = 1gt/s (note 3) 50 112 190 mv p-p d10.2 pattern, data rate = 1gt/s to 8gt/s 112 output voltage during electrical idle (ac) v tx-idle- diff-ac-p |(v out_p - v out_m )| 20 mv p-p receiver-detect pulse amplitude v tx-rcv- detect voltage change in positive direction 600 mv MAX14950A single-lane pcie equalizer/redriver maxim integrated
6 electrical characteristics (continued) (v cc = +3.0v to +3.6v, c cl = 200nf coupling capacitor on each output, r l = 50 i on each output, t a = 0 n c to +70 n c, unless oth - erwise noted. typical values are at v cc = +3.3v and t a = +25 n c.) (note 3) note 3: all devices are 100% production tested at t a = +70 n c. specifications over operating temperature range are guaranteed by design. note 4: guaranteed by design, unless otherwise noted. note 5: equivalent to same amount of deemphasis driving the input. note 6: rise and fall times are measured using 20% and 80% levels. figure 1. illustration of output deemphasis parameter symbol conditions min typ max units receiver-detect pulse width 100 ns receiver-detect retry period 200 ns control logic input-logic level low v il 0.6 v input-logic level high v ih 1.4 v input-logic hysteresis v hyst 0.1 v input pulldown resistance r pd 200 375 k i esd protection esd voltage human body model (hbm) 4 kv v low_p-p v high_p-p v high _ p- p de (d b) = 20 log v lo w_ p-p MAX14950A single-lane pcie equalizer/redriver maxim integrated
7 typical operating characteristics (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 0, oeq2 = 0, data rate = 5gt/s voltage (mv) 600 400 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc01 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 1, oeq2 = 0, data rate = 5gt/s voltage (mv) 600 400 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc04 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 0, oeq2 = 0, data rate = 5gt/s voltage (mv) 400 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc02 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 0, oeq2 = 1, data rate = 5gt/s voltage (mv) 400 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc05 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 1, oeq2 = 0, data rate = 5gt/s voltage (mv) 600 400 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc03 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 0, oeq2 = 1, data rate = 5gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc06 time (ps) MAX14950A single-lane pcie equalizer/redriver maxim integrated
8 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 1, oeq2 = 1, data rate = 5gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc07 time (ps) ineq0 = 1, ineq1 = 0, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 12in. microstrip on input, data rate = 5gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc10 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 1, oeq2 = 1, data rate = 5gt/s voltage (mv) 400 800 600 200 0 -200 -400 -800 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc08 time (ps) ineq0 = 0, ineq1 = 1, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 18in. microstrip on input, data rate = 5gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc11 time (ps) ineq0 = 1, ineq1 = 0, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 6in. microstrip on input, data rate = 5gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc09 time (ps) ineq0 = 1, ineq1 = 1, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 24in. microstrip on input, data rate = 5gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -200 -150 -100 -50 0 50 100 150 MAX14950A toc12 time (ps) MAX14950A single-lane pcie equalizer/redriver maxim integrated
9 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc13 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc16 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc14 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc17 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 250 200 150 100 50 0 -100 -50 -150 -200 -250 voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc15 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc18 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 MAX14950A single-lane pcie equalizer/redriver maxim integrated
10 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc19 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 250 200 150 100 50 0 -100 -50 -150 -200 -250 ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 0, oeq2 = 0, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 MAX14950A toc22 -100 -50 0 50 100 time (ps) voltage (mv) time (ps) -200 150 100 50 0 -50 -100 -150 MAX14950A toc20 data rate = 5gbps, output after 19in strip line, ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 500 400 300 200 100 0 -200 -100 -300 -400 -500 ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 1, oeq2 = 0, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc23 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 0, oeq2 = 0, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc21 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 1, oeq2 = 0, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc24 time (ps) MAX14950A single-lane pcie equalizer/redriver maxim integrated
11 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 0, oeq2 = 1, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc25 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 1, oeq2 = 1, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc28 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 1, oeq1 = 0, oeq2 = 1, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc26 time (ps) ineq0 = 0, ineq1 = 0, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 6in. microstrip on input, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc29 time (ps) ineq0 = ineq1 = 0, v in = 200mv p-p , oeq0 = 0, oeq1 = 1, oeq2 = 1, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc27 time (ps) ineq0 = 1, ineq1 = 0, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 12in. microstrip on input, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc30 time (ps) MAX14950A single-lane pcie equalizer/redriver maxim integrated
12 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) ineq0 = 0, ineq1 = 1, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 18in. microstrip on input, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc31 time (ps) 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) MAX14950A toc34 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 ineq0 = 1, ineq1 = 1, v in = 500mv p-p , oeq0 = oeq1 = oeq2 = 0, 24in. microstrip on input, data rate = 8gt/s voltage (mv) 400 600 200 0 -200 -400 -600 -100 -50 0 50 100 MAX14950A toc32 time (ps) 250 200 150 100 50 0 -150 -100 -100 -200 -250 voltage (mv) time (ps) MAX14950A toc35 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) MAX14950A toc33 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) max14590a toc36 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 MAX14950A single-lane pcie equalizer/redriver maxim integrated
13 typical operating characteristics (continued) (v cc = +3.3v, t a = +25 n c, unless otherwise noted.) 250 200 150 100 50 0 -150 -100 -100 -200 -250 voltage (mv) time (ps) MAX14950A toc37 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 250 200 150 100 50 0 -150 -100 -100 -200 -250 voltage (mv) time (ps) MAX14950A toc39 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 300 200 100 0 -100 -200 -300 voltage (mv) time (ps) MAX14950A toc38 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 500 400 200 300 100 0 -100 -200 -300 -400 -500 voltage (mv) time (ps) MAX14950A toc40 -100 -50 05 0 100 data rate = 8gbps, output after 19in stripline, ineq_0 = ineq_1 = 0, v in = 200mv p-p , 0eq_0 = 1, oeq_1 = 0, oeq_2 = 0 MAX14950A single-lane pcie equalizer/redriver maxim integrated
14 pin configuration pin description pin name function 1, 2, 5, 7, 10, 21, 24, 26, 29, 31 gnd ground 3 inap noninverting input, channel a 4 inam inverting input, channel a 6 en enable input. drive en low for standby mode. drive en high for normal mode. en has a 375k i (typ) internal pulldown resistor. 8 outbp noninverting output, channel b 9 outbm inverting output, channel b 11, 18, 33, 40 v cc power-supply input. bypass v cc to gnd with 0.1 f f and 0.01 f f capacitors in parallel as close as possible to the device. tqfn (5mm x 5mm) top view 35 36 34 33 12 11 13 gnd inam gnd en gnd 14 gnd outam rxdet gnd outap gnd i.c. inbp inbm 12 i.c. 45 67 27 28 29 30 26 24 23 22 oeqa0 oeqa1 v cc i.c. ineqb0 ineqb1 inap gnd 3 25 37 oeqa2 oeqb0 38 39 40 ineqa0 ineqa1 v cc oeqb1 oeqb2 *ep *connect exposed pad to gnd. v cc + v cc 32 15 i.c. i.c. 31 16 17 18 19 20 i.c. outbp outbm gnd gnd 89 10 21 gnd MAX14950A MAX14950A single-lane pcie equalizer/redriver maxim integrated
15 pin description (continued) pin name function 12 oeqb2 output deemphasis control msb, channel b. oeqb2 has a 375k i (typ) internal pulldown resistor. 13 oeqb1 output deemphasis bit 1, channel b. oeqb1 has a 375k i (typ) internal pulldown resistor. 14 oeqb0 output deemphasis control lsb, channel b. oeqb0 has a 375k i (typ) internal pulldown resistor. 15 ineqb1 input equalization control msb, channel b. ineqb1 has a 375k i (typ) internal pulldown resistor. 16 ineqb0 input equalization control lsb, channel b. ineqb0 has a 375k i (typ) internal pulldown resistor. 17, 19, 20, 30, 32, 34 i.c. internally connected. leave i.c. unconnected. 22 inbm inverting input, channel b 23 inbp noninverting input, channel b 25 rxdet receiver detection control bit. toggle rxdet to initiate receiver detection. rxdet has a 375k i (typ) internal pulldown resistor. 27 outam inverting output, channel a 28 outap noninverting output, channel a 35 oeqa0 output deemphasis control lsb, channel a. oeqa0 has a 375k i (typ) internal pulldown resistor. 36 oeqa1 output deemphasis control bit 1, channel a. oeqa1 has a 375k i (typ) internal pulldown resistor. 37 oeqa2 output deemphasis control msb, channel a. oeqa2 has a 375k i (typ) internal pulldown resistor. 38 ineqa0 input equalization control lsb, channel a. ineqa0 has a 375k i (typ) internal pulldown resistor. 39 ineqa1 input equalization control msb, channel a. ineqa1 has a 375k i (typ) internal pulldown resistor. ep exposed pad. internally connected to gnd. connect ep to a large ground plane to maximize thermal performance and ground conductivity to the device. do not use ep as the only gnd connection. MAX14950A single-lane pcie equalizer/redriver maxim integrated
16 detailed description the MAX14950A dual equalizer/redriver supports gen iii (8gt/s), gen ii (5gt/s), and gen i (2.5gt/s) pcie data rates. the device contains two identical drivers with idle/receive detect on each lane and equalization/ deemphasis/preshoot to compensate for circuit board loss. programmable input equalization circuitry reduces deterministic jitter, improving signal integrity. the device features programmable output deemphasis/preshoot, permitting optimal placement of key pcie components and longer runs of stripline, microstrip, or cable. programmable input equalization programmable input equalization for channel a is con - trolled by two bits: ineqa1 and ineqa0 and for channel b is controlled by two bits: ineqb1 and ineqb0 ( table 1 .) functional diagram table 1. input equalization ineq_1 ineq_0 input equalization (db) 0 0 5 0 1 8 1 0 12 1 1 16 equalizer equalizer r hi electrical idle detector receiver detect manager output enable en rxdet oeq_2 oeq_0 oeq_1 out_p out_m in_p ineq_1 ineq_0 in_m MAX14950A MAX14950A single-lane pcie equalizer/redriver maxim integrated
17 programmable output deemphasis programmable output deemphasis/preshoot for channel a is controlled by the three bits: oeqa2, oeqa1, oeqa0 and channel b is controlled by the three bits: oeqb2, oeqb1, oeqb0 ( table 2 .) receiver detection the device features receiver detection on each channel. upon initial power-up, if en is high, receiver detection initializes. receiver detection can also be initiated on a rising or falling edge of the rxdet input when en is high. during this time, the part remains in low-power standby mode and the outputs are squelched, despite the logic- high state of en. until a channel has detected a receiver, the receiver detection repeats indefinitely on each chan - nel. if a channel detects a receiver, the other channel is limited to a few retries. upon receiver detection, input common-mode termination and electrical idle detection are enabled ( table 3 .) electrical idle detection the device features electrical idle detection to prevent unwanted noise from being redriven at the output. when the device detects the differential input has fallen below the electrical idle low threshold, it squelches the output. for differential input signals that are above the electrical idle high threshold, the device turns on the output and redrives the signal. table 2. output deemphasis/preshoot table 3. receiver detection input function x = dont care. oeq_2 oeq_1 oeq_0 output deemphasis ratio (db) peak-to-peak swing (v) preshoot 0 0 0 0 1.0 no 0 0 1 3.5 1.0 no 0 1 0 6 1.0 no 0 1 1 6 1.2 no 1 0 0 3.5 1.0 yes 1 0 1 6 1.0 yes 1 1 0 9 0.9 yes 1 1 1 9 1.0 yes rxdet en description x 0 receiver detection is inactive x 1 following a rising edge of en signal, indefinite retry until a receiver is detected for at least one channel. retries stop a few times after any channel is detected. rising/falling edge 1 initiate receiver detection MAX14950A single-lane pcie equalizer/redriver maxim integrated
18 applications information layout circuit board layout and design can significantly affect the performance of the device. use good high-frequency design techniques, including minimizing ground induc - tance and using controlled-impedance transmission lines on data signals. power-supply decoupling capacitors must be placed as close as possible to v cc . always connect v cc to a power plane. it is recommended to run receive and transmit on different layers to minimize crosstalk. exposed-pad package the exposed-pad, 40-pin tqfn package incorporates features that provide a very low thermal resistance path for heat removal from the ic. the exposed pad on the device must be soldered to the circuit board ground plane for proper thermal performance. for more information on exposed-pad packages, refer to maxim application note hfan-08.1: thermal considerations of qfn and other exposed-paddle packages . power-supply sequencing caution: do not exceed the absolute maximum rat - ings because stresses beyond the listed ratings could cause permanent damage to the device. proper power-supply sequencing is recommended for all devices. always apply gnd then v cc before applying signals, especially if the signal is not current limited. chip information process: bicmos package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package MAX14950Actl+ 0 n c to +70 n c 40 tqfn-ep* package type package code outline no. land pattern no. 40 tqfn-ep t4055+2 21-0140 90-0002 MAX14950A single-lane pcie equalizer/redriver maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 19 ? 2013 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/11 initial release 1 4/13 updated benefits and features section, electrical characteristics table; replaced typical operating characteristics 1C12 and 21C32, updated pin configuration and pin description . updated tables 1 and 2. deleted table 4. 1, 3, 4, 5, 7, 8, 10 C 12, 14 C 17 MAX14950A single-lane pcie equalizer/redriver
20 MAX14950A single-lane pcie equalizer/redriver maxim integrated

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